CDCM6208 데이터시트 공부

 CDCM6208 데이터시트 공부하기

 

출처 : CDCM6208 데이터시트

 

 

8.4.3 Status Pins Definition

The device vitals such as input signal quality, smart mux input selection, and PLL lock can be monitored by

reading device registers or at the status pins STATUS1, and STATUS0. Register 3[12:7] allows for customization

of which vitals are mapped to these two pins. Table 12 lists the three events that can be mapped to each status

pin and which can also be read in the register space.

 

 

NOTE

It is recommended to assert only one out of the three register bits for each of the status

pins. For example, to monitor the PLL lock status on STATUS0 and the selected reference

clock sources on STATUS1 output, the device register settings would be Q3.12 = Q3.7 =

1 and Q3.11 = Q3.10 = Q3.9 = Q3.8 = 0. If a status pin is unused, it is recommended to

set the according 3 register bits to zero (for example, Q3[12:9] = 0 for STATUS0 = 0). If

more than one bit is enabled for each STATUS signal, the function becomes OR'ed. For

example, if Q3.11 = Q3.10 = 1 and Q3.12 = 0, the STATUS0 output would be high either if

the device goes out of lock or the selected reference clock signal is lost.

8.4.4 PLL Lock Detect

The PLL lock detection circuit is a digital detection circuit which detects any frequency error, even a single cycle

slip. The PLL unlock is signalized when a certain number of cycle slips have been exceeded, at which point the

counter is reset. A frequency error of 2% will cause PLL unlock to stay low. A 0.5% frequency error shows up as

toggling the PLL lock output with roughly 50% duty cycle at roughly 1/1000 th of the PFD update frequency to the

device. A frequency error of 1ppm would show up as rare toggling low for a duration of approximately 1000 PFD

update clock cycles. If the system plans using PLL lock to toggle a system reset, then consider adding an RC

filter on the PLL LOCK output (Status 1 or Status 0) to avoid rare cycle slips from triggering an entire system

reset.

 

 

 

 

 

PDN : low신호를 주면 clock generator의 전원이 꺼짐 절전모드같은거

 

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