UCD774120 데이터시트 해석(PWM INPUT)

 Interpreting UCD74120 datasheet

 

UCD74120 데이터시트를 해석하여, PWM Input 개념에 대해서 스터디 합니다.

 

 

5.2 PWM Input (PWM)

 

 

The PWM input pin accepts the digital signal from the controller that represents the desired high-side FET ontime duration.

 

PWM Input핀에서 Highside FET의 ontime을 제어하는 pwm 신호를 받음

 

This PWM input accepts 3.3-V logic levels and 5-V input levels. The SRE mode pin sets the behavior of the PWM pin. When the SRE mode pin is asserted high, the device enters synchronous mode. In synchronous mode, PWM input signal controls the timing of both the high-side gate drive and the low-side gate drive.

 When PWM is high, the high-side gate drive (HS Gate) is on and the low-side gate drive is off. When PWM is low, the high-side gate drive is off and the low-side gate drive is on.

 

SRE mode pin이 high 일 때,

PWM = high -> HS Gate on, LS Gate off

PWM = low -> HS Gate off, LS Gate on

 

 Automatic anti-cross-conduction logic monitors the gate to source voltage of the FETs to verify that the proper FET is turned OFF before the other FET is turned ON.

 

Automatic anti-cross-conduction logic이 HS와 LS FET가 ON, OFF 될 때 겹치지 않도록 모니터링 함

 

 When the SRE mode pin is asserted low, the device enters independent mode. In independent mode, the PWM input controls the high-side gate drive only. When PWM is high, the high-side gate drive is ON.

 

SRE mode pin이 low 일 때, -> only HS gate만 제어함

PWM = high -> HS Gate on

PWM = low -> HS Gate off

 

In independent mode, the SRE pin directly controlls the low-side FETs. No anti-cross-conduction logic is active in independent mode. The user must ensure that the PWM and SRE signals do not overlap.

 

Independent모드에서는 SRE핀이 LS FET를 직접 제어함

anti cross conduction logic이 동작 안하므로, 유저가 프로그램 상으로 PWM과 SRE시그날이 겹치지 않도록 주의해야 함

 

 

PWM input signal can detect when the device has entered a tri-state mode. When tri-state mode is detected, both the high-side and low-side gate drive signals remain OFF.

 

입력쪽 디바이스 출력핀이 tri-state mode에 진입하면(고장나면)

UCD74120에서 자동으로 HS, LS FET를 OFF 시킴

 

To support this tri-state mode, the PMW input pin

has an internal pull-up resistor of approximately 50-kΩ connected to the 3.3 V input. It also has a 50-kΩ pulldown resistor to ground.

 During normal operation, the PWM input signal swings below 0.8 V and above 2.5 V. If

the source driving the PWM pin enters a tri-state or high impedance state, the internal pull-up/pull-down resistors tend to pull the voltage on the PWM pin to 1.65 V.

 

PWM핀은 내부에서 풀업, 풀다운이 걸려있는데, PWM line이 tri-state나 하이임피던스 상태에 진입하면 1.65V를 띄게됨

 

 If the voltage on the PWM pin remains within the 0.8 V to 2.5V tri-state detection range for longer than the tri-state detection hold-off time (tHLD_R), then the device enters tristate mode and turns both gate drives OFF.

 

그래서 이 상태가 되면 양쪽 FET를 OFF시킴

 

 This behavior occurs regardless of the state of the SRE mode and SRE pins. When exiting tri-state mode, PWM should first be asserted low. Asserting the PWM pin low ensures that the bootstrap capacitor is recharged before attempting to turn on the high-side FET.

The logic threshold of this pin typically exhibits 900 mV of hysteresis to provide noise immunity and ensure glitchfree operation of the gate drivers.