이더넷 통신라인 라우팅 방법

 이더넷 통신라인 라우팅하는법 공부

 

출처 : 링크

 

PCB Layout Recommendations

• Keep the traces between the magnetic module and the RJ-45 jack as short as possible — their length

should be less than 25 mm (1 inch), and their impedance should be kept below 50 . No vias or layer changes are allowed. A module that integrates the RJ-45 jack with the magnetic module is preferred.

• The Tx+/Tx- and Rx+/Rx- traces should always be as short as possible (less than 25 mm or 1"). If

longer traces are absolutely required, the maximum length is limited to 75 mm (3"). The individual

trace impedance of Tx+/Tx- and Rx+/Rx- must be kept below 50 , and the differential characteristic

impedance of the pair must be 100 .

• Route each Tx+/Tx- and Rx+/Rx- pair together, keeping their separation under 0.25 mm (0.01"),

using 0.25 mm (0.01") traces. Keep the Tx+/Tx- and Rx+/Rx- trace lengths as equal as possible.

• The separation between the Tx+/Tx- and the Rx+/Rx- differential pairs must be at least 0.5 mm

(0.02"). It is best to separate them with a ground plane.

 

 

• Avoid any off-board wire assemblies. If wire assemblies are needed, use a twisted pair to connect

 

케이블 연결을 자제하고, 필요시 트위스트해야함

 

Tx+/Tx- and Rx+/Rx-, and keep their length as short as possible., no more than 75 mm (3").

• Never use right-angle traces — use 45° angles or curves in traces.

• Trace widths should not vary.

• Use precision components (1 percent or better) in the line-termination circuitry.

• Ensure that the power supply is well regulated (3.3 V DC ±5%).

 

 

88e1512 layout

 

The input and output buffers of the 1.25 GHz SERDES interface are internally terminated by 50Ω impedance. No external terminations are required.

 

MDIN, MDIP LINE은 differential로 100옴임

 

 

MDC, MDIO : 임피던스 50옴으로 맞추고 다른 특별한 제약사항 없음

 

SGMII Layout guide

 

http://www.ti.com/lit/an/sprabc1/sprabc1.pdf

 

6.2 Recommended SerDes PCB Layout Constraints

Routing requirements for the SGMII or Ethernet interface must adhere to good

engineering practices for transmission lines operating at or above 1 GHz. Specific

attention must be paid to net classes within this group and should have a high routing

priority. The device incorporates SerDes outputs and requires the use of a PHY to

interconnect to a standard RJ-45 connector.

• Each complementary device SerDes receive pair must be individually

skew-matched to within 5 ps. 5 ps equates to approximately 27.32 mils to 35.46

mils (depending on propagation delays). Example of complementary pairs

include SGMIIRXN0 & SGMIIRXP0.

• Both complementary device SerDes receive pairs must be routed on the same

layer.

• Each complementary device SerDes transmit pairs must be skew-matched to

within 5 ps. 5 ps equates to approximately 27.32 mils to 35.46 mils (depending on

propagation delays). Example of complementary SerDes pairs include:

SGMIITXN0 & SGMIITXP0.

• All complementary device transmit pairs must be routed on the same layer.

• All complementary device receive pairs (SGMIIRXN/P3:0) must be assigned to

an individual net class and routing skew must not be greater then 10 ps between

all receive pairs.

• All complementary device transmit pairs (SGMIITXN/P3:0) must be assigned to

an individual net class and routing skew must not be greater then 10 ps between

all transmit pairs.

 

• Transmit and receive signals must be referenced to parallel ground planes.

• Vias are allowed and should never exceed two per net, all nets must be balanced

and the impact of the via on timing and loading taken into account during design

and layout.

• All net signals must be referenced to a parallel ground plane.

• Differential signal routing must achieve a 100 differential impedance.

 

1) RX는 RX끼리, TX는 TX끼리 같은 layer에서 배선되어야 하며, pair line간 길이를 일치시켜야 함(35.46mils 이내로!)

2) Via는 가능한 2개를 초과하지 않도록 해주세요.

3) 모든 시그날은 gnd로 쉴딩되어야 하며, 임피던스는 100옴입니다.

 

 

mdip, mdin 핀 layout 하는법 공부

 

아래 TI기술문서 참조

http://www.ti.com/lit/an/snla079d/snla079d.pdf

 

2.1 PCB Layout Considerations • Place the 49.9 ohm,1% resistors, and 0.1μF decoupling capacitor, near the PHYTER TD+/- and RD+/- pins and via directly to the Vdd plane. • Stubs should be avoided on all signal traces, especially the differential signal pairs. See Figure 3. • Within the pairs (for example, TD+ and TD-) the trace lengths should be run parallel to each other and matched in length. Matched lengths minimize delay differences, avoiding an increase in common mode noise and increased EMI. See Figure 3. • Ideally there should be no crossover or via on the signal paths. Vias present impedance discontinuities and should be minimized. Route an entire trace pair on a single layer if possible.

 

 

 

PCB trace lengths should be kept as short as possible. • Signal traces should not be run such that they cross a plane split. See Figure 4. A signal crossing a plane split may cause unpredictable return path currents and would likely impact signal quality as well, potentially creating EMI problems.

 

• MDI signal traces should have 50 ohm to ground or 100 ohm differential controlled impedance. Many tools are available online to calculate this.