SDRAM 인터페이스 라인 라우팅을 어떻게 해야하는지 스터디   출처 : TI 기술문서   DDR3 Design Requirements for KeyStone Devices       6.3.1.3 Routing Rules – General Overview (SDRAMs) Several key points to remember when routing any signals on the application board: • Organize the power, ground, and signal planes so that you eliminate or significantly reduce the number of split or cut planes present in the design (no splits are allowed under any DDR3 routes). • It is strongly recommended that all SDRAMs are mounted on the top side of the PCB alongside the SoC for single rank designs. • Apply net classes, for example, group key signals together. • Maintain an acceptable level of skew across the entire DDR3 interface (by net class). • Use proper low-pass filtering on the Vref pins. • Follow the fly-by architecture concept for all address, command, clock, and control lines. • Increase the size of the decoupling capacitor trace width to as large as possible, keep the stub length as short as...

  USB 신호라인 라우팅 하는방법 공부   출처 :   링크       3 PCB Design Guidelines This section presents some basic guidelines for high-speed PCB design as well as some specific rules of thumb for USB full-speed design. 3.1 Recommended Routing Rules of Thumb • Route D+ and D- as 90 ohm differential pair • Always provide a good return path (ground) for current • Do not route over a gap in the reference plane • Keep away from the edge of the reference plane • Keep skew less than 400 ps • Route D+ and D- on top layer • Route D+ and D- as short as reasonably possible 3.2 PCB Stackup When designing high speed signal traces on a PCB, thought must be given to the PCB stackup. The two common approaches are to either route high speed signals on an inner layer, or to keep them on the top layer. The advantage of using an inner layer is improved noise immunity and to avoid any track impedance discontinuities when routing the signal under components, connectors etc. The benefits with out...

  PCB라우팅 방법에 대한 일반적인 공부   Place decoupling capacitors as close to the target device as possible.   -> 디커플링 커패시터는 타겟 디바이스에 가능한 가까이 배치해주세요.   Place bulk capacitors in close proximity to their respective power supply   -> Bulk cap은 power supply에 가능한 가까이 배치해주세요.   All transmission line conductors should be adjacent to its reference plane.   -> 모든 Net는 기준 GND에 인접해야 함   All microstrip nets should have a ground plane directly adjacent to the respective trace   -> Top, bottom에 위치한 net는 기준 gnd plane에 인접해야함     All stripline nets should have a ground or power plane directly adjacent (top and bottom) to the respective net where possible. If it is not possible to enclose the respective net within a ground/ground or ground/power stack-up, then at least one return path must be provided for proper operation.   ?????????   Vias and escape vias to and from the device shall be taken into account with regards to timing, reflectio...

  이더넷 통신라인 라우팅하는법 공부   출처 :   링크   PCB Layout Recommendations • Keep the traces between the magnetic module and the RJ-45 jack as short as possible — their length should be less than 25 mm (1 inch), and their impedance should be kept below 50 . No vias or layer changes are allowed. A module that integrates the RJ-45 jack with the magnetic module is preferred. • The Tx+/Tx- and Rx+/Rx- traces should always be as short as possible (less than 25 mm or 1"). If longer traces are absolutely required, the maximum length is limited to 75 mm (3"). The individual trace impedance of Tx+/Tx- and Rx+/Rx- must be kept below 50 , and the differential characteristic impedance of the pair must be 100 . • Route each Tx+/Tx- and Rx+/Rx- pair together, keeping their separation under 0.25 mm (0.01"), using 0.25 mm (0.01") traces. Keep the Tx+/Tx- and Rx+/Rx- trace lengths as equal as possible. • The separation between the Tx+/Tx- and the Rx+/Rx- differential pairs must be at least 0....