USB3.0 통신라인 아트웍 가이드 공부
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3 PCB Design Guidelines
This section presents some basic guidelines for high-speed PCB design as well as some specific rules
of thumb for USB full-speed design.
3.1 Recommended Routing Rules of Thumb
• Route D+ and D- as 90 ohm differential pair
• Always provide a good return path (ground) for current
• Do not route over a gap in the reference plane
• Keep away from the edge of the reference plane
• Keep skew less than 400 ps
• Route D+ and D- on top layer
• Route D+ and D- as short as reasonably possible
3.2 PCB Stackup
When designing high speed signal traces on a PCB, thought must be given to the PCB stackup. The
two common approaches are to either route high speed signals on an inner layer, or to keep them on
the top layer. The advantage of using an inner layer is improved noise immunity and to avoid any track
impedance discontinuities when routing the signal under components, connectors etc. The benefits with
outer layer routing is to avoid vias which easily cause discontinuities in the return current path unless
special care is taken. For USB signals on EFM32 microcontrollers the preferred solution is normally to
route the signal on an outer layer, as PCB traces usually are short.
Independently of whether the signals are routed on an inner or outer layer, they should always be routed
over a solid reference plane. Thus the PCB should have minimum 2 layers.
3.3 Routing
When a signal trace on a PCB is long relative to the highest frequency component of the signal,
transmission line effects must be taken into consideration. The transition between when a wire should
be modeled as a transmission line and a wire with "no length" is gradual, but common practice is to apply
transmission line models when the trace length is more than 1/10th of the wavelength of the highest
frequency component on the trace. For traces shorter than this, it is safe to assume that the voltage
level is the same over the entire trace.
For digital signals the shortest wavelength is dependent on the signal bandwidth which again depends
on the shortest rise and fall times. Faster rise times equals higher frequency content. A common
approximation is that
where tr is the minimum rise time from 10-90%. USB specifies a minimum rise time of 4 ns, which equals
a maximum signal bandwidth of 87.5 MHz or a minimum wavelength of 1.7 meters on a typical PCB
trace. Thus if PCB traces are shorter than 170 mm, it can be argued that the characteristic impedance
of a track is not important. However, good design practice is to route USB signals as an impedance
matched differential pair according to specification.
3.3.1 Differential Pairs
The USB data lines, D- and D+, should be routed as a differential pair. The trace impedance should be
matched to the USB cable differential impedance, which is nominally 90 ohms for the signal pair.
...the world's most energy friendly microcontrollers
2013-09-16 - an0046_Rev1.01 9 www.silabs.com
The impedance of a signal track is mainly determined by its geometry (i.e. trace width and height above
the reference plane) and the dielectric constant of the material between the traces and a reference plane.
When two tracks are closely spaced, they will be coupled and the differential impedance will also be
dependent on the distance between the two tracks comprising the pair.
In general one can say that if the two traces of a differential pair is spaced far apart, the differential
impedance will be twice the impedance of each trace. I.e. the two traces can be considered a shunt
impedance. When the distance between the two traces is reduced, coupling between the traces will
cause the differential impedance to decrease. Thus to create a differential pair with 90 ohms impedance,
the single ended impedance of each trace should be above 45 ohms. Reducing the trace width will
increase the single-ended impedance while reducing the distance between the traces in a pair reduces
the impedance. This allows routing of very closely spaced differential pairs that use little PCB area. Note,
however that thin traces will be more difficult to manufacture, and that for high frequencies loss due to
skin effect comes into play.
Most PCB design tools support differential pairs, and can create such pairs with specified parameters.
If such a tool is not available, there are many online impedance calculators that can calculate track
parameters.
To avoid differential imbalance, skew (or trace length difference) between the two traces in a differential
pair should be under control. A common rule of thumb is to keep the skew less than 1/10th of the fastest
rise time. For USB full-speed this translates to 400 ps or 60 mm. However, this is the total skew over the
entire communication link so skew in the USB cable as well as in the other communicating party must
also be included. According to the USB specification the maximum allowed skew in a cable is 100 ps,
which leaves a maximum of 300 ps (45 mm) of skew to be distributed amongst the host and device.
Still, as you never know the characteristics of the other end, good design practice is to keep skew at
a reasonable minimum.
When high speed signals are routed from one layer to another, care should also be taken to provide
a path for the return signals. Remember that even differential signals use a reference plane as return
path. This is particularly important when designing PCBs with many layers.
http://www.ti.com/lit/ug/sllu149e/sllu149e.pdf
TUSB73x0 Board Design and Layout Guidelines
User's Guide
5.3 High-Speed Differential Routing
The high-speed differential pair (USB_DM and USB_DP) is connected to a type A USB connecter. The
differential pair traces should be routed with 90 Ω ±15% differential impedance. The high-speed signal pair
should be trace length matched. Max trace length mismatch between high speed USB signal pairs should
be no greater than 150 mils. Keep total trace length to a minimum, if routing longer than eight inches
contact TI to address signal integrity concerns.
Route differential traces first. Route the differential pairs on the top or bottom layers with the minimum
amount of vias possible. No termination or coupling caps are required. If a common mode choke is
required then place the choke as close as possible to the USB connector signal pins. Likewise ESD
clamps should also be placed as close as possible to the USB connector signal pins (closer than the
choke).
For more detailed information, you may also see the USB 2.0 Board Design and Layout Guidelines
(SPRAAR7) which describes general PCB design and layout guidelines for the USB 2.0 differential pair
(DP/DM).
5.4 SuperSpeed Differential Routing
SuperSpeed consists of two differential routing pairs, a transmit pair (USB_SSTXM and USB_SSTXP) and
a receive pair (USB_SSRXM and USB_SSRXP). Each differential pair traces should be routed with 90 Ω
±15% differential impedance. The high-speed signal pair should be trace length matched. Maximum trace
length mismatch between SuperSpeed USB signal pairs should be no greater than 5 mils. The total length
for each differential pair can be no longer than eight inches, this is based on the SS USB compliance
channel spec, and should be avoided if at all possible. TI recommends that the SS diff pairs be as short
as possible.
The transmit differential pair does not have to be the same length as the receive differential pair. Keep
total trace length to a minimum. Route differential traces first. Route the differential pairs on the top or
bottom layers with the minimum amount of vias possible. The transmitter differential pair requires 0.1-μF
coupling capacitors for proper operation. The package/case size of these capacitors should be no bigger
than 0402. C-packs are not allowed. The capacitors should be placed symmetrically as close as possible
to the USB connector signal pins.
If a common mode choke is required, then place the choke as close as possible to the USB connector
signal pins (closer than the transmitter capacitors). Likewise, ESD clamps should also be placed as close
as possible to the USB connector signal pins (closer than the choke and transmitter capacitors).
It is permissible to swap the plus and minus on either or both of the SuperSpeed differential pairs. This
may be necessary to prevent the differential traces from crossing over one another. However it is not
permissible to swap the transmitter differential pair with the receive differential pair.
It is recommended to use a 2010 pad for the inside pins provided no pad is used for adjacent pins.
Instead use a pad on one of the inside pins then for the next pad route the trace between the outer pins to
a via.
There is enough space to route a 3.78-mil trace between the outside pads while leaving 5-mil spacing
between the trace and pad, it is then possible to increase the trace width to 4 mils after the breakout. In
Figure 5-3 the red pads are USB_SS_RXP/USB_SS_RXN and the blue pads are
USB_SS_TXP/USB_SS_TXN.