Introduction to Intel Memory Solutions

The following topics provide an overview of Intel® 's External Memory Interface solutions.

Intel provides the fastest, most efficient, and lowest latency memory interface IP cores.Intel® 's external memory interface IP is designed to easily interface with today's higher speed memory devices.

Intel® supports a wide variety of memory interfaces suitable for applications ranging from routers and switches to video cameras. You can easily implement Intel® ’s intellectual property (IP) using the memory IP core functions through the Quartus® Prime software. The Quartus® Prime software also provides external memory toolkits that help you test the implementation of the IP in the FPGA device.

Refer to the External Memory Interface Spec Estimator page for the maximum speeds supported by Intel® FPGAs.

Related Information

External Memory Interface Spec Estimator

Introduction to Intel FPGA IP Cores

Creating Version-Independent IP and Qsys Simulation Scripts

Project Management Best Practices

Memory Solutions

Intel® FPGAs achieve optimal memory interface performance with external memory IP.The IP provides the following components:

Physical layer interface (PHY) which builds the data path and manages timing transfers between the FPGA and the memory device.
Memory controller which implements all the memory commands and protocol-level requirements.
Multi-port front end (MPFE) which allows multiple components inside the FPGA device to share a common memory interface. The MPFE is available in Intel® Arria V and Intel® Cyclone V devices.

Figure 1. Memory Interface Architecture

Intel® 's FPGAs provide two types of memory solutions, depending on device family: soft memory IP and hard memory IP. The soft memory IP gives you the flexibility to design your own interfaces to meet your system requirements and still benefit from the industry leading performance. The hard memory IP is designed to give you a complete out-of-the-box experience when designing a memory controller.

The following table lists features of the soft and hard memory IP.

Table 1. Features of the Soft and Hard Memory IPSoft Memory IPHard Memory IP

Includes hardened PHY with soft controller.
Allows maximum flexibility in choosing location, size, and configuration of the memory interface.
Can optionally be used in PHY-only mode to integrate with a custom user-designed controller.

Includes hardened PHY, hardened controller, and hardened MPFE.
Supports maximum performance and lowest latency.
May have a fixed location on a device and/or a fixed pinout for address and command signals.
Simplifies the overall integration of a memory interface and provides an out-of-the-box experience for every designer.

Intel® provides modular memory solutions that allow you to customize your memory interface design to a variety of configurations:

PHY with your own controller
PHY with Intel® controller
PHY with Intel® controller and a multiport front end. (MPFE is a configurable block available for hard interfaces in Arria V and Cyclone V devices.)

You can also build a custom PHY, a custom controller, or both, as desired.

한마디로 FPGA 내에서, 메모리에 빠르게 인터페이스 할 수 있는 IP코어를 제공하고, 이를 external memory interface라고 부름

2) External Memory Interface Pins

External Memory Interface Pins

Note: Altera® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.

Table 5. External Memory Interface PinsPin NamePin FunctionsPin DescriptionConnection Guidelines

DQS[#]	I/O,bi-directional	Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry.	Connect unused pins as defined in the Intel®Quartus® Prime software.
DQSn[#]	I/O,bi-directional	Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry.	Connect unused pins as defined in the Intel®Quartus® Prime software.
DQ[#]	I/O,bi-directional	Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, if you plan on migrating to a different memory interface that has a different DQ bus width, you will need to reevaluate your pin assignments. Analyze the available DQ pins across all pertinent DQS columns in the pin list.	Connect unused pins as defined in the Intel®Quartus® Prime software.
DQS[#]_[#]	I/O, bidirectional	Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic.	Connect unused pins as defined in the Intel®Quartus® Prime software.
DQSn[#]_[#]	I/O, bidirectional	Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry.	Connect unused pins as defined in the Intel®Quartus® Prime software.
DQ[#]_[#]_[#]	I/O, bidirectional	Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, if you plan on migrating to a different memory interface that has a different DQ bus width, you will need to reevaluate your pin assignments. Analyze the available DQ pins across all pertinent DQS columns in the pin list.	Connect unused pins as defined in the Intel®Quartus® Prime software.
DM[#]_[#]	I/O, Output	Optional write data mask, edge-aligned to DQ during write.	Connect unused pins as defined in the Intel®Quartus® Prime software.
RESET_N_0	I/O, Output	Active low reset signal.	Connect unused pins as defined in the Intel®Quartus® Prime software.
A_[#]	I/O, Output	Address input for DDR3 SDRAM.	Connect unused pins as defined in the Intel®Quartus® Prime software.
BA_[#]	I/O, Output	Bank address input for DDR3 SDRAM.	Connect unused pins as defined in the Intel®Quartus® Prime software.
CK_[#]	I/O, Output	Input clock for external memory devices.	Connect unused pins as defined in the Intel®Quartus® Prime software.
CK_N_[#]	I/O, Output	Input clock for external memory devices, inverted CK.	Connect unused pins as defined in the Intel®Quartus® Prime software.
CKE_[#]	I/O, Output	High signal enables clock, low signal disables clock.	Connect unused pins as defined in the Intel®Quartus® Prime software.
CS_N_[#]	I/O, Output	Active low chip select.	Connect unused pins as defined in the Intel®Quartus® Prime software.
CA_[#]_[#]	I/O, Output	Command and address input for LPDDR3 SDRAM.	Connect unused pins as defined in the Intel®Quartus® Prime software.
ODT_[#]	I/O, Output	On die termination signal to set the termination resistors to each pin.	Connect unused pins as defined in the Intel®Quartus® Prime software.
WE_N_0	I/O, Output	Write-enable input for DDR3 SDRAM and all supported protocols.	Connect unused pins as defined in the Intel®Quartus® Prime software.
CAS_N_0	I/O, Output	Column address strobe for DDR3 SDRAM.	Connect unused pins as defined in the Intel®Quartus® Prime software.
RAS_N_0	I/O, Output	Row address strobe for DDR3 SDRAM.	Connect unused pins as defined in the Intel®Quartus® Prime software.
ALERT_N_0	I/O, Input	Alert input that indicate to the system's memory controller that a specific alert or event has occurred.	Connect unused pins as defined in the Intel®Quartus® Prime software.
PAR_0	I/O, Output	Command and Address Parity Output.	Connect unused pins as defined in the Intel®Quartus® Prime software.
CFG_N_0	I/O, Output	Configuration bit.	Connect unused pins as defined in the Intel®Quartus® Prime software.
LBK[#]_N_0	I/O, Output	Loop-back mode.	Connect unused pins as defined in the Intel®Quartus® Prime software.

각 pin에 대한 설명은 위와 같고, 아트웍 시 특별히 주의해야 할 부분은 bidirectional line 인 것으로 생각됩니다.

3) EMIF 라인 아트웍 하기(Layout EMIF Nets)

Determining Your Board Layout

Before you can specify parameters for your external memory interface, you must determine the necessary board-related settings for your IP.

Review the recommended board design guidelines for your external memory interface protocol.
Select the termination scheme and drive strength settings for all the memory interface signals connected between the FPGA and the external memory device.
Perform board-level simulations to determine the optimal settings for best signal integrity, appropriate timing margins, and sufficient eye opening.
- Successful board-level simulation is often an iterative process, experimenting with different combinations of drive strength, terminations, IP board parameters, and timing results.
- Ensure that your simulation applies the latest FPGA and memory device IBIS models, board trace characteristics, drive strength, and termination settings.
- You might identify board-level timing uncertainties such as crosstalk, ISI, or slew rate deration during simulation. If you identify such timing uncertainties, adjust the Board Settings in the IP Catalog with the slew rate deration, ISI/crosstalk, and board skews to ensure the accuracy of the TimeQuest timing margins report.

Related Information

DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines

Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines

LPDDR2 SDRAM Board Design Guidelines

QDR II and QDR IV SRAM Board Design Guidelines

RLDRAM II and RLDRAM 3 Board Design Guidelines