KeyStone II Architecture Serializer/Deserializer (SerDes) User's Guide 공부하기   출처 :   Ti 기술문서   9.2 Recommended SerDes PCB Layout Constraints Routing requirements for the SGMII or Ethernet interface must adhere to good engineering practices for transmission lines operating at or above 1 GHz. Specific attention must be paid to net classes within this group and should have a high routing priority. The device incorporates SerDes outputs and requires the use of a PHY to interconnect to a standard RJ-45 connector. • Each complementary device SerDes receive pair must be individually skew-matched to within 1 ps. 1 ps equates to approximately 5.5 mils to 7.1 mils (depending on propagation delays). Example of complementary pairs include SGMIIRXN0 and SGMIIRXP0. • Each complementary device SerDes receive pairs must be routed on the same layer. • Each complementary device SerDes transmit pairs must be skew-matched to within 1 ps. 1 ps equates to approximately 5.5 mils to 7.1 m...

  Intel cyclone 10 GX 시리즈 중 하나인 10CX105YU484I6G의 EMIF line 회로설계에 대한 스터디 자료입니다.  자료는 해당 EVM에서 제공하는 기술문서를 참조했습니다.  1) EMIF (External Memory InterFace)란    Introduction to Intel Memory Solutions The following topics provide an overview of   Intel®   's External Memory Interface solutions. Intel   provides the fastest, most efficient, and lowest latency memory interface IP cores.Intel®   's external memory interface IP is designed to easily interface with today's higher speed memory devices. Intel®   supports a wide variety of memory interfaces suitable for applications ranging from routers and switches to video cameras. You can easily implement   Intel®   ’s intellectual property (IP) using the memory IP core functions through the   Quartus®   Prime   software. The   Quartus®   Prime   software also provides external memory toolkits that help you test the implementation of the IP in the FPGA devi...