Keystone 2 Serdes라인 유저가이드 공부

 KeyStone II Architecture Serializer/Deserializer (SerDes) User's Guide 공부하기

 

출처 : Ti 기술문서

 

9.2 Recommended SerDes PCB Layout Constraints

Routing requirements for the SGMII or Ethernet interface must adhere to good engineering practices for

transmission lines operating at or above 1 GHz. Specific attention must be paid to net classes within this

group and should have a high routing priority. The device incorporates SerDes outputs and requires the

use of a PHY to interconnect to a standard RJ-45 connector.

• Each complementary device SerDes receive pair must be individually skew-matched to within 1 ps.

1 ps equates to approximately 5.5 mils to 7.1 mils (depending on propagation delays). Example of

complementary pairs include SGMIIRXN0 and SGMIIRXP0.

• Each complementary device SerDes receive pairs must be routed on the same layer.

• Each complementary device SerDes transmit pairs must be skew-matched to within 1 ps. 1 ps equates

to approximately 5.5 mils to 7.1 mils (depending on propagation delays). Example of complementary

SerDes pairs include: SGMIITXN0 and SGMIITXP0.

• Each complementary device SerDes transmit pairs must be routed on the same layer.

• Transmit and receive signals must be referenced to parallel ground planes.

• Vias are allowed and all nets must be balanced and the impact of the via on timing and loading taken

into account during design and layout.

• Differential signal routing must achieve a 100-Ω differential impedance.

 

 

 

 

 

Baud definition

 

Baud was the prevalent measure for data transmission speed until replaced by a more accurate term, bps (bits per second). One baud is one electronic state change per second. Since a single state change can involve more than a single bit of data, the bps unit of measurement has replaced it as a better expression of data transmission speed.

The measure was named after a French engineer, Jean-Maurice-Emile Baudot. It was first used to measure the speed of telegraph transmissions.

 

 

 

10.2 Recommended SerDes PCB Layout Constraints

Routing requirements for the PCIe interface shall adhere to good engineering practices for transmission

lines operating above 5 GHz. Specific attention shall be paid to net classes within this group and should

have a high routing priority (if this interface is used).

• Each complementary PCIe SerDes receive pair shall be individually skew matched to within 1 ps. 1 ps

equates to approximately 5.464 mils to 7.092 mils (depending on propagation delays). Example of

complementary pairs include PCIERXN0 and PCIERXP0.

• Each complementary PCIe SerDes receive pairs shall be routed on the same layer.

• Each complementary PCIe SerDes transmit pair shall be individually skew matched to within 1 ps. 1 ps

equates to approximately 5.464 mils to 7.092 mils (depending on propagation delays). Example of

complementary pairs include PCIETXN0 and PCIETXP0.

• Each complementary PCIe SerDes transmit pairs shall be routed on the same layer.

• All complementary PCIe receive pairs PCIERXN/P1:0 shall be assigned to an individual net class

where routing skew shall not be greater than 100 ps between all receive pairs. (The full link budget is

2UI+500ps so lane to lane skew can be larger if additional system analysis is completed.)

• All complementary PCIe transmit pairs PCIETXN/P1:0 shall be assigned to an individual net class and

routing skew shall not be greater than 100 ps between all transmit pairs. (The full link budget is

2UI+500ps so lane to lane skew can be larger if additional system analysis is completed.)

• Transmit and receive signals must be referenced to parallel ground planes.

• Vias are allowed and should never exceed four per net, all nets must be balanced and the impact of

the via on timing, reflections, and loading taken into account during design and layout. This interface

should be modeled to assure functionality.

• Differential signal routing must achieve a 100-Ω differential impedance