LMZ21700 LAYOUT(ARTWORK)

LMZ21700

10 Layout

10.1 Layout Guidelines

The PCB layout is critical for the proper operation of any DC/DC switching converter. Although using modules

can simplify the PCB layout process, care should still be taken to minimize the inductance in the high di/dt loops

and to protect sensitive nodes. The following guidelines should be followed when designing a board layout with

the LMZ21700:

10.1.1 Minimize the High di/dt Loop Area

The input capacitor, the VIN terminal, and the GND terminal of the LMZ21700 form a high di/dt loop. Place the

input capacitor as close as possible to the VIN and GND terminals of the module IC. This minimizes the area of

the high di/dt loop and results in lower inductance in the switching current path. Lower inductance in the

switching current path translates to lower voltage spikes on the internal switch node and lower noise on the

output voltage. Make the copper traces between the input capacitor and the VIN and GND terminals wide and

short for better current handling and minimized parasitic inductance.

10.1.2 Protect the Sensitive Nodes in the Circuit

The feedback node is a sensitive circuit which can pick up noise. Make the feedback node as small as possible.

This can be achieved by placing the feedback divider as close as possible to the IC. Use thin traces to the

feedback pin in order to minimize the parasitic capacitance to other nodes. The feedback network carries very

small current and thick traces are not necessary. Another sensitive node to protect is the VOS pin. Use a thin

and short trace from the VOUT terminal of the output capacitor to the VOS pin. The VOS pin is right next to the

GND terminal. For very noisy systems, a small (0402 or 0201) 0.1-μF capacitor can be placed from VOS to GND

to filter high frequency noise on the VOS line.

10.1.3 Provide Thermal Path and Shielding

Using the available layers in the PCB can help provide additional shielding and improved thermal performance.

Large unbroken GND copper areas provide good thermal and return current paths. Flood unused PCB area with

GND copper. Use thermal vias to connect the GND copper between layers.

The required board area for proper thermal dissipation can be estimated using the power dissipation curves for

the desired output voltage and the package thermal resistance vs. board area curve. Refer to the power

dissipation graphs in the Typical Characteristics section. Using the power dissipation (PDISS) for the designed

input and output voltage and the max operating ambient temperature TA for the application, estimate the required

thermal resistance RθJA with the following expression.

RθJA - REQUIRED≤ (125ºC – TA) / PDISS