Routing Clock signal(Ti application note study)
Ti application note study -> Routing Clock signal
10.2.1 Clock and High Performance Transmission Lines - Microstrip versus Stripline
Clock nets (and most other high-performance nets) are typically designed for either a microstrip or stripline
topology. Figure 32 shows the difference between a microstrip and a stripline topology.
Figure 32. Stripline and Microstrip Topologies
The most obvious difference between these two topologies is the location of the respective net (trace). In
a stripline topology (left side) the net or trace is embedded in the PCB and usually between ground or
power layers. In the microstrip topology (right side), the net or trace is on an outer layer and adjacent to a
power or ground plane.
There are several reasons why one (stripline or microstrip) topology would be selected over the other, key
factors determining which topology is used include:
• Interconnection - The number of pins on the interconnecting devices may limit the width of traces on
the outer layers.
• Performance - High speed signals should not be routed on multiple layers, they should generally be
routed on the top layers.
• EMI - Where emissions or the susceptibility to spurious radiation may impact signal integrity, stripline
topologies are recommended.
• Timing - Propagation delays differ between microstrip and stripline topologies, the use of either must
be comprehended for any and all timing-critical nets.
• Routing - The routing of high-speed clock signals is critical to a functional design. Proper return
current paths to minimize switching noise is essential. Routing clocks that are > 250 MHz should be
done using only a microstrip topology as long as they are < 2 inches (50.8 mm) in length.
sdram clock쪽은 기본적으로 inner layer를 통해 배선되고, top, bottom 에 노출되는 부분은 50.8mm 이내로 해야 합니다.
1) Single-ended clock signals should have additional spacing to other nets to avoid crosstalk or coupling.
Single ended clock 시그널 라인은 다른 class의 라인과 크로스톡 방지를 위해 이격을 좀 더 둬야 합니다. (크로스톡 : 다른 Net에서 발생하는 방사노이즈가 영향을 주는 현상)
Keep high-speed signals away from the edges of the PCB. If necessary, pin the edges of the PCB to prevent EMI emissions.
High speed line은 pcb의 edge부분에서 이격이 있어야함
All clock trace routes must be as straight as possible, minimize or eliminate serpentine routing
-> 모든 Clock trace는 직선으로 배선되고, 사선배선 경로를 최대한 줄여야 합니다.
Optimize all single-ended nets, minimize lengths where possible (as long as they do not violate any net class requirements or violate timing conditions)
-> Single-ended net의 길이를 최소화 해주세요.
Route single-ended nets perpendicular or orthogonal to other single-ended nets to prevent coupling.
-> 커플링 방지를 위해, single-ended net들은 직각으로 배선해주세요.
All clocks should be routed on a single layer
All high-performance clock signals should be routed on the same layer where possible. If not possible,
then the impact of multiple layers on performance, propagation delays, and signal integrity must be
taken into account.
-> 모든 clock signal은 같은 층에 배선해주세요.
Nets within a particular net class should have a matched number of vias if used (vias are not recommended if possible).
-> 가능한 Via가 없지만, 만약 사용된다면, 같은 class내의 Net들은 같은 Via개수를 가지게 해주세요.
Clock nets, if routed internally, must be captured between two planes. Do not have two clock routing layers adjacent to one another.
Clock net가 inner layer에서 배선될 시, net들 끼리는 인접한 layer에서 배선되지 않도록 해주세요.
Clock nets involved in synchronous communications must have identical number of vias and be skewmatched within 5% of the total clock period.
-> ?????????????
Vias and terminations (if required) must be positioned in locations such that reflections do not impact signal quality or induce an unwanted change of state.
->
The target impedance for a single-ended clock net is 50 Ω and the PCB impedance must be ± 5% or 47.5 Ω to 52.5 Ω.
The target impedance for a differential ended clock nets is 100 Ω and the differential PCB impedance must be ± 5% or 95.0 Ω - 105 Ω.
-> 싱글 ended 일 때 - 임피던스 50옴, differential 일 때 - 임피던스 100옴
All microstrip clock lines must have a ground plane directly adjacent to the clock trace
-> Top, Bottom 에 clock line이 배선될 땐, 반드시 ground 층과 맞닿아야함
All stripline clock lines must have a ground or power planes directly adjacent (top and bottom) to the clock trace.
-> ????????
Terminate any single-ended clock signals.
-> single-ended clock signal은 터미네이션 처리해야함
터미네이션 : http://www.rfdh.com/bas_rf/begin/isolator.php3
Confirm whether or not the differential clock sources require terminations
-> diff 라인에서 터미네이션 저항이 필요한지 확인해야함
A ground plane must be located directly below all clock sources (oscillators, crystals).
-> ground plane은 반드시 클락소스 바로 밑에 위치해야 함
No digital signals must be routed underneath clock sources
-> 디지털 시그날은 clock source 밑으로 배선하지 말아야 함
Clock nets (source to target) must be as short as possible – emphasis on reflections
-> clock nets는 가능한 짧아야 합니다.
Complementary differential clock nets must be routed with no more then two vias
-> Complementary differential clock nets는 Via를 2개이상 사용하지 말아주세요.
Escape vias from the device or clock source must be of either via-in-pad or dog-bone type design.
Dog-bone designed escapes must be short enough to ensure any reflections do not impact signal
quality.
-> ????????????
The number of vias used in complementary differential clock pairs should be identical.
-> diff clock line에 사용되는 via는 반드시 그 수가 같아야함
Differential clock signals (complementary nets) must be skew-matched to within a maximum 5 pS of one another.
-> 스큐매칭?????
hardware design guide for keystone ii device
3.5.1.1 Clock Tree Layout Requirements
Key considerations when routing between clock sources and the device include the
problems associated with reflections, crosstalk, noise, signal integrity, signal levels,
biasing, and ground references. To establish the optimal clocking source solution, the
requirements in the sections below should be followed.
As with all high-performance applications, it is strongly recommended that you model
(simulate) the clocking interface to verify the design constraints in the end-use
application. Application board stack up, component selection, and the like all have an
impact on the characteristics identified below.
See the Clocking Design Guide for KeyStone Devices Application Report (SPRABI4) for
additional details pertaining to routing and interconnection.
3.5.2 Clock Tree Trace Width
Clocking trace widths are largely dependent on frequency and parasitic coupling
requirements for adjacent nets on the application board. As a general rule of thumb,
differential clock signals must be routed in parallel and the spacing between
the differential pairs should be a minimum 2 times (2×) the trace width. Single-ended
nets should have a spacing of 1.5× the distance of the widest parallel trace width.
3.5.3 Clock Tree Spacing
Given the variation in designs, the minimum spacing between any adjacent signals
should be a minimum of 1× the width. A spacing of 1× is typically suitable for control
signals (or static signals) and not data or clock nets. Single-ended or differential nets
should be spaced from other nets a minimum of 1.5× and 2× respectively. A detailed
cross-talk and coupling analysis (signal integrity) should be performed before any
design is released to production. An additional rule of thumb would be to maintain
trace spacing three times the dielectric height (reduces ground bounce and crosstalk).
http://www.ti.com/lit/an/sprabi4/sprabi4.pdf
Spacing – Single-ended traces, especially those of the high-speed type, should be spaced properly from other signals to avoid coupling. Differential traces should have proper line-to-line spacing. An increase in the separation between parallel traces reduces the coupling effects. In microstrip designs, coupling is a linear function to spacing. In a stripline configuration, coupling is approximately a square function of spacing. Minimal line-to-line separation can account for a two- to four-fold reduction in potential crosstalk.