SPI 통신라인 라우팅 가이드

Spi 통신라인 라우팅 가이드 공부

Clock Signal Routing

In high speed synchronous data transfer, good signal integrity in a PCB design is of importance, especially for the

clock signal. When routing the clock signal, special cares should be taken. The following practices are

recommended.

 Run the clock signal at least 3x of the trace width away from all other signal traces. This helps to keep clock signal clean from noise. See Figure 3.

 Use as less via(s) as possible for the whole path of clock signal. Via will cause impedance change and signal reflection.

 Run the clock trace as straight as possible and avoid using serpentine routing. See Figure 4.

 Keep a continuous ground in the next layer as reference plane.

 Route the clock trace with controlled impedance.

Figure 3. Separate Clock From Other Signals

1) Clock trace와 Signal trace 사이 간격은 Clock trace 두께의 3배로 한다.

2) Via사용을 최소화하고, 가능한한 직선으로 배선한다.

3) 임피던스 : 50옴

Data Signal Routing

The FL-P Flash has a 4-bit data bus, IO0 - IO3. In order to keep the correct timing for the data transfer, in the PCB

routing, the data traces should match the time delay with the clock trace from the host controller to the Flash. The

data signals should be routed with the traces of controlled impedance to reduce the signal reflection. It should be

avoided to route the traces with 90 angle corner. The recommendation is to cut the corner and smooth the trace

when trace route needs to change direction. Figure Figure 5 shows the example of trace routing at the corner. To

further improve the signal integrity, it should be considered to avoid using multiple signal layers for data signal

routing. All signal traces should have a continuous reference plane.

Figure 5. Signal Routing at the Corner

1) line이 90도로 꺾이면 안됨